SFMDTY=0, SFMDV=0x00
Clock Control Register
SFMDV | Serial interface reference cycle select. (Pay attention to irregularities.) 0 (0x00): 2 PCLKA 1 (0x01): 3 PCLKA (divided by an odd number) 2 (0x02): 4 PCLKA 3 (0x03): 5 PCLKA (divided by an odd number) 4 (0x04): 6 PCLKA 5 (0x05): 7 PCLKA (divided by an odd number) 6 (0x06): 8 PCLKA 7 (0x07): 9 PCLKA (divided by an odd number) 8 (0x08): 10 PCLKA 9 (0x09): 11 PCLKA (divided by an odd number) 10 (0x0A): 12 PCLKA 11 (0x0B): 13 PCLKA (divided by an odd number) 12 (0x0C): 14 PCLKA 13 (0x0D): 15 PCLKA (divided by an odd number) 14 (0x0E): 16 PCLKA 15 (0x0F): 17 PCLKA (divided by an odd number) 16 (0x10): 18 PCLKA 17 (0x11): 20 PCLKA 18 (0x12): 22 PCLKA 19 (0x13): 24 PCLKA 20 (0x14): 26 PCLKA 21 (0x15): 28 PCLKA 22 (0x16): 30 PCLKA 23 (0x17): 32 PCLKA 24 (0x18): 34 PCLKA 25 (0x19): 36 PCLKA 26 (0x1A): 38 PCLKA 27 (0x1B): 40 PCLKA 28 (0x1C): 42 PCLKA 29 (0x1D): 44 PCLKA 30 (0x1E): 46 PCLKA 31 (0x1F): 48 PCLKA |
SFMDTY | Duty ratio correction function select for the QSPCLK signal when devided by an odd number 0 (0): Make no correction 1 (1): Make correction |